Fpga Implementation of Micro-rotation Selection Algorithm for Efficient Cordic Architecture

This paper presents a FPGA implementation of micro-rotation selection algorithm for CORDIC architecture. By selection of third order of approximation of Taylor series, the proposed CORDIC circuit meets the accuracy requirements, and attains the desired range of convergence. The proposed architecture is a scale-free design which provides the flexibility to manage the number of iterations depending on area, latency, and accuracy requirements. It is based on high speed leading one-bit position detection algorithm which avoids the complex search algorithms for identifying the micro-rotations. The area and timing issues overcome, to make an efficient design which is optimized and compact. Compared to existing iterative architecture the proposed one has 2.3% lower slice-delay product with 33% increase in speed on Xilinx Spartan 2E XC2S200E device.